Qnity Electronics Inc. unveiled a materials platform designed to accelerate advanced semiconductor packaging for AI-driven systems, the company said on Monday. The Wilmington, Delaware-based firm introduced the solution at the Heterogeneous Integration Global Summit during SEMICON Taiwan 2026, targeting 2.5D, 3D and panel-level architectures used in high-performance computing and memory applications.
The platform consolidates metallization, bumping, dielectric and fine-line patterning technologies to meet demand for higher interconnect density and bandwidth in AI chip designs. Key components include copper-to-copper direct and hybrid bonding, tin-silver micro-bumps and high-resolution dielectric processes capable of 2 µm line/space metallization.
Jason Chuang, Packaging Polymer Segment Director at Qnity, will present details at TaiNEX 2 on September 1 during a session at exhibition booth S7930 in the Materials Pavilion. The company highlighted support for Chip-on-Wafer-on-Substrate, Embedded Multi-die Interconnect Bridge and high-bandwidth memory configurations.
Qnity’s product portfolio includes Intervia CB1000+ and CB3000 copper solutions for within-die uniformity and low-impurity deposition, alongside the Solderon TS8000 series for tin-silver micro-bump plating in high-bandwidth memory applications. The Riston WBR5000 dry film photoresist supports copper pillar plating with film thickness ranging from 200 to 320 µm for 2.5D packaging, while the Cyclotene dielectric addresses fan-out panel-level and advanced substrate needs.
Chuck Xu, President of Interconnect Solutions at Qnity, emphasized the shift toward system-level solutions in customer requirements.
